5/26/2023 0 Comments Simple delay line based oscillator![]() The circuit has been simulated in Cadence Virtuoso® for 90nm Process Design Kit (PDK) with an input signal of 1GHz at 1.1Volt power supply (Vdd). A small-signal model for this proposed circuit is presented to note the related parameters for achieving the near-symmetric output rise/fall time. Therefore, in this article, we have unearthed a delay circuit which is expected to generate nearly equal rise/fall time at the output having a unique setup of delivering variable delay. However, most of the variable delay elements are unable to impart the matching of output rise/fall time. For clock signals, it is important to achieve equal rise/fall time in order to support correct level-triggered based on-chip sequential operation. The function of these kinds of circuit is to transfer the input signal at the output with an added amount of timing delay. The design of active delay circuits and variable delay elements are being investigated over the years as they are popular inside the integrated circuit (IC) chip, for example in on-chip clock distribution. This dependency is different for the case of a voltage- or current mode configuration of the ring. In particular, we show that the biasing of the ring has an enormous impact on power efficiency of the ring. In contrast to these independencies, we identify several important dependencies. most performance metrics are independent on the number of VCO stages and the external load capacitance on the VCO nodes. ![]() Our study highlights several important independencies: e.g. We do this both through theoretical modeling as well as through simulations, which are in good agreement with each other. Next, we study the main analog performance figures: the effective oscillation frequency (which affects the quantization noise of a VCO ADC), the input referred noise and the power efficiency both for voltage and current control. First, we show that they can be accurately modeled by an equivalent 2-terminal diode-like element. In this work, we focus on the three most relevant pseudo-digital ring oscillator circuits for VCO A/D conversion. The multi-phase sub-outputs are the inherent divided output (÷ 5 or ÷ 7) that can be directly utilized in a PLL to save area and power. The tuning range covers 1.7 to 3.5 GHz (68.5%) over VDD = 0.7 to 1 V. The measured f₁/f³ is 150 kHz at 3.47 GHz, which is 6.2x less than that of a typical 5-stage RVCO. The prototype is a 35-stage dual-mode TI-RVCO occupying 0.003 mm² in 65 nm CMOS, and has a selectable TI factor of 5 and 7. A reconfigurable TI factor extends the tuning range over the same range of supply voltage (VDD). The critical block is the phase combiner, which features a timing window to minimize the delay offset and mismatch. Such features are achieved by substantially increasing the number of delay stages in a RVCO, such that the rich multi-phase sub-outputs can be combined through a time-interleaved method, generating a high-frequency output with a significantly lowered 1/f³ phase noise corner (f₁/f³). This paper describes a time-interleaved (TI) ring-VCO (RVCO) exhibiting an improved phase noise over a wide range of frequency offsets, an extended tuning range and an inherent divided output.
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